1. Field of the Invention
The present invention generally relates to multiple-valued logic circuits, and more particularly to a multiple-valued logic circuit having a circuit formation in which a plurality of inputs are connected by capacitance coupling and having a function of generating an output based on a weighted linear sum thereof. More specially, the present invention is concerned with a circuit formation called a neuron MOS (Metal Oxide Semiconductor) circuit. In view of circuit functions, the present invention relates to a multiple-valued logic circuit in which three or more voltage levels can be set on one signal line and thus has a function higher than that of normal binary logic circuits.
2. Description of the Related Art
As is known, a neuron-MOS circuit has a formation in which the gate of a MOS transistor is floating and input signals are capacitively coupled to the MOS transistor. Hence, a channel of the transistor is formed in accordance with a weighted linear sum of input voltages. When such a neuron-MOS circuit is applied to a neural network, an FPGA (Flat Pin Grid Array) or the like, the resultant circuit can be simplified. The following document discloses the detail of a neuron-MOS circuit as described above: H. Ishi et al., "Hardware-Backpropagation Learning of Neuron MOS Neural Networks", 1992 IEDM Tech. Dig., pp. 435-pp. 438.
FIG. 1 shows an example of a neuron-MOS circuit. The circuit shown in FIG. 1 a complementary type source-grounded amplifier which includes a P-channel MOS transistor and an N-channel MOS transistor. The two MOS transistors have a common floating gate FG, to which input signals V1-Vn (n is an arbitrary integer) are capacitively coupled. The potential of the floating gate FG is based on a weighted linear sum of the input voltages V1-Vn. An output voltage Vout has a characteristic in which the output voltage Vout sharply falls in response to a value of the floating gate potential.
Generally, a multiple-valued logic circuit is formed by an ECL (Emitter-Coupled Logic) circuit or an IIL circuit (Integrated Injection Logic) circuit, these circuits being made up of bipolar transistors. These bipolar circuits operate in the current mode, by which it is easy to obtain a linear sum. However, there is a disadvantage in that a large amount of power is consumed.
Recently, it has been proposed that the neuron-MOS circuit is applied to the multiple-valued circuits. In the neuron-MOS circuit, it is possible to easily obtain the linear sum of the input voltages in the voltage mode. Hence, it is considered that the application of the neuron-MOS circuit to the multiple-valued circuits contributes to reducing power consumption and simplifying the circuit configuration.
The neuron-MOS circuit shown in FIG. 1 is a binary output circuit which has a disadvantage in that the output voltage is switched from a high level (V.sub.DD) to a low level (V.sub.SS) in response to a slight change of the input potential.
An improved neuron-MOS circuit capable of generating multiple-valued outputs has been proposed which is intended to overcome the above disadvantage.
FIG. 2 is a circuit diagram of a complementary-type source-follower amplifier. The source of an N-channel MOS transistor and the source of a P-channel MOS transistor are connected together. The multiple-valued output voltage Vout is obtained at the sources of these transistors. Such a neuron-MOS circuit is described in detail in T. Shibata et al., "Neuron MOS Voltage-Mode Circuit Technology for Multiple-Valued Logic", IECE TRANS. ELECTRON., Vol. E76-C, No. 3, March 1993, pp. 347-pp. 356. A multiple-valued memory using the neuron-MOS circuit shown in FIG. 2 has been proposed in R. Au et al., "Neuron-MOS Multiple-Valued Memory Technology for Intelligent Data Processing", International Conference on Advanced Microelectronic Devices and Processing, pp. 80-pp. 85.
However, the multiple-valued output neuron-MOS circuit shown in FIG. 2 has a disadvantage in that the gain to the potential of the floating gate FG is approximately equal to 1 due to the source-follower configuration and the gain with respect to the individual input voltages V1-Vn is lower than 1. This disadvantage is a serious problem encountered when a multiple-valued logic circuit is formed using the neuron-MOS circuit shown in FIG. 2. Hence, the neuron-MOS circuit can be applied to a limited field.